The present invention relates generally to integrated circuits and their formation, and more particularly to the formation of diamond thin film trench for use as a capacitor forming part of, for example, a DRAM in a bipolar, C-MOS or other such submicron integrated circuit or as a means for electrically isolating adjacent electronic components of such a circuit, for example adjacent transistors.
The formation of integrated circuits using bipolar, C-MOS or other such submicron technology is well known in the art. As an example, FIG. 1 diagramatically illustrates part of an integrated circuit 10 which has been formed in accordance with conventional prior art practices. This integrated circuit is shown including, among other components, a pair of adjacent transistors T1 and T2 formed within a cooperating tub or well 12 of p or n doped silicon which, in turn, is established in a silicon or other suitable dielectric substrate. The field oxide is grown on a suitable silicon or other such substrate (not shown). In order to ensure that the two transistors T1 and T2 function reliably and independently, they must be electrically isolated from one another. Theretofore, one common way of accomplishing this was to form a relatively thick layer of field oxide, for example on the order of 5000 .ANG., between the adjacent transistors. More recently, in order to scale down the bipolar, C-MOS and other such submicron technologies to levels below 0.5 micron levels, it has been necessary to scale down the field oxide islands that isolate p and n wells or separate electronic components within the same tub or well. In high density gate/memory arrays, the scaling has forced designers to move away from field arrays to fieldless arrays. As a result, rather than establishing a layer of field oxide between wells or electronic components such as transistors T1 and T2 in the case of integrated circuit 10, the use of an isolation trench arrangement has been proposed more recently. Such a trench arrangement is shown in FIG. 1 at 16. This arrangement includes a trench which is cut or otherwise formed by standard means, specifically by means of reactive ion etching. Once the trench is established, successive layers of silicon dioxide (or other such composite dielectric capable of being 10 deposited or thermally grown) and nitride 18 and 20 are grown on the walls within the trench and the latter is then filled with polysilicon, undoped TEOS or other suitable dielectric substance 22 in order to planarize the overall arrangement, as illustrated in FIG. 1.
The same type of trench configuration described immediately above has been proposed heretofore in the formation of storage capacitors for use as part of DRAMs. However, in the case where the trench arrangement is to be used as a capacitor, the internal trench walls are ion-implanted with the appropriate dopant which forms the bottom plate of the capacitor before the silicon dioxide and nitride layers 18 and 20, respectively, are formed and the trench is filled with polysilicon which serves as the top plate or electrode of the capacitor.
While isolation trench arrangement and capacitor trench arrangements of the types described immediately above may be improvements over the use of the field oxides in scaled down integrated circuit technologies, they do have certain drawbacks. In the case of isolation trench arrangement 16, the trench and specifically the oxide/nitride layers are located directly adjacent the n +or p +junctions of its adjacent transistors. When the transistors are biased, active (high electron) trapping takes place at the well (silicon)/trench (silicon oxide) interface. This, in turn, can cause junction walk-out which means that the breakdown of the junction will actually change as the device is turned on, thereby causing it to turn on at different voltages, for example 5 volts at one time and 5.6 volts at another time. In the case of the trench capacitor arrangement described above, the relatively low dielectric constant of the silicon dioxide forming part of the capacitor severely limits its storage capacity and severely limits the speed of the DRAM which includes the capacitor.
An unsuccessful conventional attempt to form a diamond coated trench in a semiconductor substrate will be described with reference to FIGS. 2a-e. Initially, a surface of a semiconductor wafer 222 is covered with a photoresistive material. Selected sections of the photoresist are exposed and developed by photolithography. The developed photoresist is then removed to leave a hard mask pattern 220 of unexposed photoresist on the wafer 222 as shown in FIG. 2a.
The semiconductor wafer surface is then bombarded by ions in a highly anisotropic reactive ion etching to form a trench masked out by the hard mask 222. The ions eat away silicon in the wafer substrate while leaving the photoresist essentially unscathed. During trench formation, the reactive ion etching may impart some random roughness on a trench bottom surface. However, the roughness is not predetermined or controlled. Standard photoresist solvents burn off residual photoresist in a cleaning or "ashing". The resulting trench 224 with a bottom surface 226 is shown in FIG. 2b.
Diamond 228 is applied non-selectively to the wafer 222 to the cover the trench 228 and on numerous areas over the wafer surface outside the trench as shown in FIG. 2c. Chemical vapor deposition, acetylene torch, and decomposition methods all deposit diamond both inside and outside the trench.
A photoresist mask 230 is then applied to cover the diamond coated trench. The removal of diamond from planar surfaces is well know within the art to be an extremely difficult problem. The unwanted diamond on the outside areas is removed by any of various strong wet or dry etching techniques such as sputtering while the mask 230 prevents diamond 228 in the trench from being etched away. Unfortunately, the strong etchings damage the substrate 222 and thus worsen the isolation problems which the trench formation was supposed to improve. The mask formed in step 211 is removed in step 213 to leave a diamond coated trench. The process 200 ends in a step 214.
FIG. 2e illustrates the resulting diamond coated trench 224. "Stringer" diamond fragments 232 remain about the trench lip. The strong etchings which remove the diamond outside the trench 224 leave damage areas 234 on the wafer surface. The diamond 228 in the trench is not guaranteed to have a uniform thickness.
The resulting trench and substrate in FIG. 2e are in practice not useful in integrated circuits. The stringers 232 can easily break away from the lip during integrated circuit manufacture and cause serious contamination problems. Even if the stringer problem were overcome, the trench 224 could not be used as an isolation trench because the damaged areas 234 degrade component isolation rather than improve it. The trench 224 would also fail in a capacitor arrangement both because of the damaged areas 234 and because the thickness of the diamond cannot be predetermined.
A method of forming a diamond coated trench which could selectively deposit a uniform diamond layer with a predetermined thickness would be advantageous. By selectively forming diamond only in the trench, the stringer and substrate damage problems from etching away diamond from surfaces outside the trench would be obviated. If a uniform, predetermined diamond layer thickness could be selected and then applied to the trench, accurate integrated circuit capacitors could be made using diamond as the trench capacitor dielectric. The disadvantages of silicon oxide and silicon nitride capacitors mentioned above would be avoided.